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EECS Faculty Candidate Seminar- Xunzhao Yin

Xunzhao Yin,
Ph.D. Candidate, University of Notre Dame

11:00am, Tuesday, February 12

Min H. Kao room 435


Vertically integrated efforts for energy-efficient computing

As Moore’s law based device scaling and accompanying performance scaling trends slow down, there is increasing interest in new technologies and computational paradigms that enable faster and more energy-efficient information processing. Meanwhile, there is growing evidence that in the context of traditional Boolean circuits and/or von Neumann architectures, it will be challenging for beyond-CMOS devices to compete with the CMOS technology. Exploiting the unique characteristics of emerging devices -- especially in the context of alternative circuits and architectural paradigms -- has the potential to offer orders of magnitude improvement in terms of energy and/or performance. In order to realize the full advantage of beyond-CMOS devices, integrated research efforts that span from devices to circuits to architectures to algorithms to applications are indispensable.

In this talk, I will show how my research work has contributed to such vertically integrated efforts in achieving significant improvements in energy and performance. I will focus on one case study to demonstrate our co-design and co-optimization approaches across the device, circuit, architecture and application levels. Specifically, I will highlight a ternary content addressable memory (TCAM) design based on Ferroelectric FETs (FeFETs). TCAMs are desirable in many applications including IP routers and cognitive learning. Using models calibrated by experimentally demonstrated devices as well as detailed circuit simulations, we show that vertically integrated design approach for TCAM could help to enable orders of magnitude improvements when considering application-level tasks in the machine learning domain, etc.

Xunzhao Yin received his B.S. degree in the department of Electronic Engineering from Tsinghua University, China, in 2013. He is currently the Ph.D. candidate in the department of Computer Science and Engineering, University of Notre Dame, Indiana, USA. 

His research interests include efficient circuit and architecture designs with both CMOS and emerging technologies, mix-signal circuit design for non-Von Neumann computing paradigms and hardware security. He has participated in several large projects sponsored by DARPA/NSF/SRC, e.g., Center for Low Energy System Technology (LEAST), Center for Extremely Energy Efficient Collective Electronics (EXCEL), and Application and Systems driven Center for Energy-Efficient Integrated NanoTechnologies (ASCENT), where he is exploring novel circuits and architectures based on beyond-CMOS technologies and novel computing paradigms. He has published 11 conference papers at ICCAD, DATE, GLSVLSI, etc, and 4 journal papers at TVLSI, TCASII, JETC, etc. He received the Outstanding Research Assistant Award in the department of CSE at University of Notre Dame, 3rd place award for 3-minute-thesis Competition at University of Notre Dame, and Bronze medal of Student Research Competition at ICCAD2016.

Tuesday, February 12, 2019 at 11:00am to 12:00pm

Min H. Kao Electrical Engineering and Computer Science, 435
1520 Middle Drive, Knoxville, TN 37996

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