The Future is Frozen: Cryogenic CMOS for High Performance Computing

Abstract:

The demand for High-Performance-Compute (HPC) has grown over 100x in the last decade and has well surpassed the rate of growth in transistor density per classical Moore’s Law. To make matters worse, the dimensional scaling that has traditionally enabled Moore’s Law has, itself, plateaued. Reduction in the historical rate of performance gain across technology nodes, the inability to scale down the threshold voltage—and consequently the supply voltage—without increasing the leakage currents, and increasing power density forcing throttling of processor clock speed have all contributed to inefficient data centers gobbling the world's electricity. Cryogenic CMOS is a radical and disruptive technology that operates at very low temperatures and can provide significant power and performance benefits.

The steep subthreshold switching characteristics, accompanied by other performance boosters like improved mobility, ultra-low leakage, lower wiring resistance, and reduced self-heating make cryogenic CMOS a promising option. In this talk, I will discuss how the superior device characteristics can aid power performance benefits across compute, connect, and storage paradigms of modern-day processors. First, I will present the design-technology co-optimization study conducted on a 64-bit Arm Core and standard SRAM cells to demonstrate improvement in performance while scaling down the power and draw insights into the results. Next, I will review chip results of unique circuits like cryogenic gain cell based embedded DRAM which can thrive in the low temperature environment. Finally, I will discuss the CMOS interconnect modeling and its effect on power and performance. I will then examine the cooling cost for such systems and propose my future research to build and sustain the next generation compute systems using cryogenic-CMOS, 3-D integrated systems and quantum computing.

Biography:

Rakshith Saligram is a final year PhD candidate in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology, Atlanta USA, advised by Prof. Arijit Raychowdhury. He earned his bachelor's in engineering (BE) in electronics and communication from BMS College of Engineering, Bangalore, India and MS honors in electrical engineering from University of Southern California, Los Angeles, USA. He worked as graphics hardware engineer at Intel Corporation prior to joining PhD and at Arm Inc and IMEC Nanoelectronics Design Center as a  research intern during his PhD. His current research focuses on Cryogenic CMOS, Heterogeneous Integration, Low Power Digital and Mixed Signal Circuit Design, and Quantum Interface Circuits. He is the recipient of multiple internal recognitions at Intel Corporation, the 2020 GT-ORNL seed research grant, and finalist in 2022 Qualcomm Innovation Fellowship Award.